Name: Suzhou cycas Microelectronics Co., Ltd.
Address: 1st floor,B06 building,No.2,Fuxing Road,Zhangjiagang Economic Development Zone,Jiangsu Province 215600PRC
Gate oxide and implants
In the semiconductor manufacturing industry, different processes are usually divided into four categories: deposition, removal, pattern structure, change of electrical performance.
Deposition is a process of growing, covering or transferring materials on a wafer. Available techniques include physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy and the latest atomic layer deposition. Removal is a process of removing material from a wafer, including etching (dry or wet) and polishing.
Pattern structure is to shape or change the accumulation of materials, usually known as lithography. For example, in the traditional lithography technology, the wafer is coated with a layer of photoresist, focusing, centering and moving the mask with the equipment, and the lithography is completed under the short wave light; the photoresist in the exposed area is washed away with the developer. After etching or other processes, plasma etching machine is used.
The change of electrical performance has always been made by doping transistor source (initially by diffusion furnace, later by ion implantation). These doping processes are realized by diffusion furnace annealing or rapid annealing with advanced equipment; annealing is to activate implanted dopants. The change in electrical properties now extends to the reduction of the dielectric constant of the material through a process of low insulator exposure to ultraviolet light. Modern chips have up to 11 metal production levels, more than 300 process steps.
The former process refers to the formation of transistors on silicon. The original wafer is grown by high purity, and there are almost no defects in the epitaxial silicon layer. Prior to the most advanced logic device, silicon epitaxy step, execution techniques improve transistor performance. One way is to introduce a silicon variant, such as SiGe deposition. Once the epitaxial silicon is deposited, the lattice is stretched to improve the electron mobility. Another method, called insulating silicon technology, is to insert an insulating layer between the original silicon wafer and the silicon epitaxial thin layer, which leads to the reduction of the creation of parasitic effect transistors.
The subsequent process of gate oxide and implants gate oxidation and injection front-end surface engineering is to grow gate dielectric layer (traditional silica), gate mode, source and consumption area mode, and then implant or dopant diffusion to obtain the required complementary electrical performance. In dynamic random access memory (DRAM) devices, storage capacitors are also assembled, which are usually stacked on the memory (Qimonda, the now bankrupt DRAM manufacturer), to embed these capacitors into the silicon surface etching groove).
once various semiconductor devices are produced, they must be connected to form the required circuit. This series of process steps are collectively referred to as post process (not to be confused with the packaging and testing phases). The latter process involves the creation of wires isolated by a dielectric layer. Silicon dioxide or silicon glass are usually used as insulating materials. Although the dielectric constant of materials provided by chip manufacturers is lower than 2.2, recently low dielectric materials (such as silicon carbon oxide) are used, and the typical dielectric constant is 2.7 (silicon dioxide is 3.9).
Interconnection a standard battery is interconnected by four layers of flat copper conductors down to polysilicon (pink), well (grey) and substrate (green). Before, the wires were made of aluminum. First, a layer of aluminum is deposited. After photolithography and etching, the aluminum wire is left, and then the insulation material covers the exposed aluminum wire. Different metal layers are interconnected by etched holes (called "through holes") on the insulating material, and tungsten is deposited into the through holes by chemical vapor deposition technology; this method is also applied to many memory chip manufacturing, such as dynamic random access memory (DRAM), because the number level of interconnection is very small (currently no more than four).
In recent years, with the increase of the number of transistors and the level of interconnection, the time delay of the circuit becomes so important that the wiring materials (from aluminum to copper) and the dielectric layer materials (from silicon dioxide to new low insulator) need to be changed. The improvement of this property also reduces the cost and process steps through the metal inlay process. As the number of interconnects increases, the front layer needs to be flattened to ensure the subsequent front plane lithography. Without this step, the horizontal plane will become more and more curved, affecting the lithography extension, thus interfering with the lithography ability. Although dry etching is still applicable when the number of interconnections is no more than three, polishing is the main method to achieve flatness.
The high serialization processing of wafer test wafer increases the measurement demand between different process steps. Wafer test and measurement equipment is used to verify that the wafer is not damaged in the process before the test; if there are too many unqualified grains in one wafer, the whole wafer will be scrapped and the subsequent process cost will be reduced.
Once the device test is completed, the semiconductor devices will go through various electrical tests to determine whether they can work normally. The qualified rate of products directly affects the manufacturer's earnings. The manufacturer usually keeps their earnings secret, but it can be as low as 30%. The semiconductor production line uses the electronic tester to test the chip through the probe pressed on the grain, and the tester marks the unqualified chip.
At present, according to the predetermined test range, through the electronic dye marking function, the data stored in the central computer is screened out (i.e. divided into virtual dustbins). Finally, according to the selected data, a grain distribution map is drawn to track and mark the unqualified chips. This grain distribution map can also be used for wafer assembly and packaging. The packaged chip also needs to be tested to prevent wire breaking or analog performance changes, which is called "final test". Usually, the cost of factory testing is a few cents per second. Test time is from a few milliseconds to a few seconds. Test time is reduced by optimizing test software. Because many testers have enough resources to perform most or all of the synchronous tests, multi chip (multi site) testing is also feasible. The design of chips often has "testability" features such as scan chain or "self check" function to test quickly, so as to reduce the test cost. In some designs that use specialized simulation plant processes, the resistance values are achieved by laser fine-tuning during testing to achieve the expected, closely distributed values. A good design will test and statistically test the ultimate properties of silicon (at high temperature and under extreme process conditions). Most designs deal with at least 64 limit states. After the grain is ready for testing, it is usually necessary to separate and divide the wafer after thinning. This process is called wafer cutting. Only good, scratch free chips can be packaged. Package plastic or ceramic package includes grain assembly, welding grain and pin on package shell as well as grain sealing. Small wires are used to connect pins and grains. Previously, wires were welded by hand, but now they are replaced by special machines. Traditionally, these wires are made of gold, leading to tinned copper "lead frames"; lead is toxic, so lead-free "lead frames" are now mandatory by RoHS. Another packaging technology -- chip level packaging. Like most packages, the volume of plastic dual in-line package is many times larger than the actual chip, and the chip size of chip level package is almost the same as the grain size; before slicing, the chip level package shell can be designed. After packaging, the chip needs to be tested to ensure that it is not damaged during the packaging process and the connection between grains and pins is correct. Then the model of the chip is marked by laser on the packaging shell.