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Classification of different processes in semiconductor manufacturing在半導體製造業中,各種不同的工藝的分類

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Classification of different processes in semiconductor manufacturing在半導體製造業中,各種不同的工藝的分類

發布日期:2018-01-04 作者:www.tonertimes.com 點擊:

在半導體製造業中,各種不同的工藝通常分為四大類:沉積、移除、圖案結構、改變電氣性能。


沉積是一種在晶片上生長、覆蓋或轉移材料的工藝。可用的技術包括物理氣相沉積、化學氣相沉積、電化學沉積、分子束外延以及Z新的原子層沉積。

移除是一種去除晶片上材料的工藝,其中包括刻蝕工藝(幹法或濕法)以及拋光。

圖案結構是塑造或改變堆積的材料,通常被稱為光刻。例如,傳統的光刻技術,晶片塗上一層光刻膠,利用設備進行聚焦、對中、移動掩板,在短波光下完成光刻;用顯影劑衝走暴露區域的光刻膠。在刻蝕或其他工藝後,利用等離子刻蝕機

改變電氣性能曆來是用摻雜晶體管源(Z初由擴散爐,後來通過離子注入)。這些摻雜工藝通過擴散爐退火,或用先進的設備進行快速退火實現;退火是為了激活植入的摻雜物。改變電氣性能現在也延伸到通過低絕緣體暴露在紫外線工藝降低材料的介電常數。

現代芯片有多達11種金屬生產水平,超過300道工藝處理步驟。

等離子刻蝕機

前道工藝過程

前道工藝是指在矽上形成晶體管。原始的晶片是由高純度生長而來,實際上通過外延矽層幾乎沒有缺陷。在Z先進的邏輯器件,矽外延步驟之前,執行技巧提高晶體管的性能。其中一個方法是引入一個矽變體,如矽鍺沉積。一旦外延矽沉積,晶格拉伸,從而提高電子遷移率。另一種方法稱為絕緣矽技術,是在原始矽片與矽外延薄層之間插入絕緣層,該方法導致減少寄生效應晶體管的創建。

Gate oxide and implants


柵氧化和注入

前端表麵工程後續的工藝是增長閘極介電層(傳統的二氧化矽),門的模式,源和消耗區域的模式,以及隨後的植入或摻雜物擴散獲得所需的互補的電氣性能。在動態隨機存取記憶體(DRAM)器件中,存儲電容也被組裝,通常堆放存取記憶體上麵(現已倒閉的DRAM製造商奇夢達)實現了將這些電容器嵌入到矽表麵刻蝕槽)。



後道工藝過程

金屬化:一旦各種半導體器件被生產,它們必相互連接形成所需的電路。這一係列的工藝步驟被統稱為後道工藝(不要與封裝和測試階段混淆)。後道工藝過程包含創建被介電層隔離的金屬線。絕緣材料通常用二氧化矽或矽玻璃,盡管芯片製造商提供的材料介電常數低於2.2,但是近來低介電材料被使用(例如矽碳氧化物),典型的介電常數為2.7(二氧化矽是3.9)。


互連

一個標準電池通過四層平麵型銅導線互連,下至多晶矽(粉紅色),井(灰色)和基質(綠色)。

以前,金屬線都是鋁製的。首先沉積一層鋁層,經過光刻、刻蝕,留下鋁線,然後絕緣材料覆蓋裸露的鋁線。不同的金屬層利用絕緣材料上的蝕孔(稱為“貫穿孔”)相互連接,通過化學氣相沉積技術將鎢沉積到貫穿孔中;這種方法還應用於很多內存芯片製造中,例如動態隨機存取存儲器(DRAM),因為其互連的數量級別很小(目前不超過四)。

近年來,隨著邏輯器件增加大量的晶體管,互連數量級別也大大增加,以至於如今使用微處理器互連,線路的時間延遲變得如此重要,以至於需要改變布線材料(從鋁到銅),以及介質層材料的改變(從二氧化矽到新的低絕緣體)。這種性能的提高,同時也通過金屬鑲嵌工藝降低了成本,減少了工藝步驟。隨著互連數量級別的增加,需要整平前層以確保後續前平麵光刻。缺少這個步驟,水平麵會越來越彎曲,影響光刻外延,從而幹擾光刻的能力。盡管當互連數量級別不超過三時,依然適用幹法刻蝕處理,但拋光是實現平整的主要處理方法。


晶圓測試

晶片的高度序列化性質工藝處理增加了不同工藝步驟間的計量需求。晶圓測試計量設備用於驗證晶片在測試之前的工藝過程中沒有損壞;如果在一個晶片有太多的晶粒不合格,整個晶片將報廢,降低後續工藝成本。


器件測試

一旦前道工藝完成,半導體器件會經過各種各樣的電氣測試,以確定她們是否能夠正常工作。產品的合格率直接影響到製造商的收益,製造商對他們的收益率通常是保密的,但它可以低至30%。

半導體生產線利用電子測試儀,通過壓在晶粒上的探針,對芯片進行測試,測試儀器對不合格的芯片打點做標記。目前, 根據預定的測試範圍,通過電子染料標記功能,將中央計算機儲存的數據篩選出來(即分為虛擬垃圾箱)。Z終根據篩選的數據繪製成一張晶粒分布圖,用來跟蹤和標記不合格的芯片。這張晶粒分布圖還可以使用在晶片組裝和封裝上。封裝後的芯片同樣需要測試,防止導線斷路或模擬性能改變,這被稱為“Z終測試”。

通常,工廠測試的成本費用每秒幾分錢。測試時間從幾毫秒到幾秒,通過優化測試軟件來減少測試時間。因為許多測試人員有足夠的資源來執行大部分或所有的同步測試,多個芯片(多站點)測試也是可行的。

芯片的設計常常有“測試性特征”如掃描鏈或“自檢“功能快速測試,以降低測試成本。在某些使用專門的模擬工廠工藝的設計中,測試期間通過激光微調,以實現預期的、緊密分布的阻值。

良好的設計會測試和用統計學的方式測試極限性能(在高溫狀態下以及極端的工藝條件測試矽的極限性能)。大多數設計至少應對64種極限狀態。


晶粒準備

測試後,通常需要經過減薄後再將晶片拆分、劃分晶粒,這一過程稱為晶片切割。隻有好的,無劃痕的芯片才進行封裝。


封裝

塑料或陶瓷封裝包括晶粒裝配、焊接晶粒與封裝外殼上的引腳以及晶粒密封。細小的導線用來連接引腳和晶粒。以前是通過手工焊接導線,如今使用專用的機器代替。傳統上,這些導線由黃金構成,通向使用鍍錫的銅“引線框”;而鉛是有毒的,因此無鉛“引線框”現已被RoHS強製使用。

另一種封裝技術--芯片級封裝。如同大多數封裝,塑料雙列直插式封裝體積比實際的晶片大很多倍,而芯片級封裝芯片尺寸與晶粒大小幾乎一致;在劃片前,芯片級封裝外殼就可以設計出來。

封裝後芯片需要測試以確保在封裝過程中未被破壞、晶粒與引腳間的連接正確。然後在封裝外殼上用激光標記芯片的型號。

     In the semiconductor manufacturing industry, different processes are usually divided into four categories: deposition, removal, pattern structure, change of electrical performance. 

    Deposition is a process of growing, covering or transferring materials on a wafer. Available techniques include physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy and the latest atomic layer deposition. Removal is a process of removing material from a wafer, including etching (dry or wet) and polishing. 

   Pattern structure is to shape or change the accumulation of materials, usually known as lithography. For example, in the traditional lithography technology, the wafer is coated with a layer of photoresist, focusing, centering and moving the mask with the equipment, and the lithography is completed under the short wave light; the photoresist in the exposed area is washed away with the developer. After etching or other processes, plasma etching machine is used. 

   The change of electrical performance has always been made by doping transistor source (initially by diffusion furnace, later by ion implantation). These doping processes are realized by diffusion furnace annealing or rapid annealing with advanced equipment; annealing is to activate implanted dopants. The change in electrical properties now extends to the reduction of the dielectric constant of the material through a process of low insulator exposure to ultraviolet light. Modern chips have up to 11 metal production levels, more than 300 process steps. 

   The former process refers to the formation of transistors on silicon. The original wafer is grown by high purity, and there are almost no defects in the epitaxial silicon layer. Prior to the most advanced logic device, silicon epitaxy step, execution techniques improve transistor performance. One way is to introduce a silicon variant, such as SiGe deposition. Once the epitaxial silicon is deposited, the lattice is stretched to improve the electron mobility. Another method, called insulating silicon technology, is to insert an insulating layer between the original silicon wafer and the silicon epitaxial thin layer, which leads to the reduction of the creation of parasitic effect transistors. 

  The subsequent process of gate oxide and implants gate oxidation and injection front-end surface engineering is to grow gate dielectric layer (traditional silica), gate mode, source and consumption area mode, and then implant or dopant diffusion to obtain the required complementary electrical performance. In dynamic random access memory (DRAM) devices, storage capacitors are also assembled, which are usually stacked on the memory (Qimonda, the now bankrupt DRAM manufacturer), to embed these capacitors into the silicon surface etching groove). 

Metallization: 

once various semiconductor devices are produced, they must be connected to form the required circuit. This series of process steps are collectively referred to as post process (not to be confused with the packaging and testing phases). The latter process involves the creation of wires isolated by a dielectric layer. Silicon dioxide or silicon glass are usually used as insulating materials. Although the dielectric constant of materials provided by chip manufacturers is lower than 2.2, recently low dielectric materials (such as silicon carbon oxide) are used, and the typical dielectric constant is 2.7 (silicon dioxide is 3.9). 

Interconnection a standard battery is interconnected by four layers of flat copper conductors down to polysilicon (pink), well (grey) and substrate (green). Before, the wires were made of aluminum. First, a layer of aluminum is deposited. After photolithography and etching, the aluminum wire is left, and then the insulation material covers the exposed aluminum wire. Different metal layers are interconnected by etched holes (called "through holes") on the insulating material, and tungsten is deposited into the through holes by chemical vapor deposition technology; this method is also applied to many memory chip manufacturing, such as dynamic random access memory (DRAM), because the number level of interconnection is very small (currently no more than four). 

In recent years, with the increase of the number of transistors and the level of interconnection, the time delay of the circuit becomes so important that the wiring materials (from aluminum to copper) and the dielectric layer materials (from silicon dioxide to new low insulator) need to be changed. The improvement of this property also reduces the cost and process steps through the metal inlay process. As the number of interconnects increases, the front layer needs to be flattened to ensure the subsequent front plane lithography. Without this step, the horizontal plane will become more and more curved, affecting the lithography extension, thus interfering with the lithography ability. Although dry etching is still applicable when the number of interconnections is no more than three, polishing is the main method to achieve flatness.

       The high serialization processing of wafer test wafer increases the measurement demand between different process steps. Wafer test and measurement equipment is used to verify that the wafer is not damaged in the process before the test; if there are too many unqualified grains in one wafer, the whole wafer will be scrapped and the subsequent process cost will be reduced. 

     Once the device test is completed, the semiconductor devices will go through various electrical tests to determine whether they can work normally. The qualified rate of products directly affects the manufacturer's earnings. The manufacturer usually keeps their earnings secret, but it can be as low as 30%. The semiconductor production line uses the electronic tester to test the chip through the probe pressed on the grain, and the tester marks the unqualified chip. 

    At present, according to the predetermined test range, through the electronic dye marking function, the data stored in the central computer is screened out (i.e. divided into virtual dustbins). Finally, according to the selected data, a grain distribution map is drawn to track and mark the unqualified chips. This grain distribution map can also be used for wafer assembly and packaging. The packaged chip also needs to be tested to prevent wire breaking or analog performance changes, which is called "final test". Usually, the cost of factory testing is a few cents per second. Test time is from a few milliseconds to a few seconds. Test time is reduced by optimizing test software. Because many testers have enough resources to perform most or all of the synchronous tests, multi chip (multi site) testing is also feasible. The design of chips often has "testability" features such as scan chain or "self check" function to test quickly, so as to reduce the test cost. In some designs that use specialized simulation plant processes, the resistance values are achieved by laser fine-tuning during testing to achieve the expected, closely distributed values. A good design will test and statistically test the ultimate properties of silicon (at high temperature and under extreme process conditions). Most designs deal with at least 64 limit states. After the grain is ready for testing, it is usually necessary to separate and divide the wafer after thinning. This process is called wafer cutting. Only good, scratch free chips can be packaged. Package plastic or ceramic package includes grain assembly, welding grain and pin on package shell as well as grain sealing. Small wires are used to connect pins and grains. Previously, wires were welded by hand, but now they are replaced by special machines. Traditionally, these wires are made of gold, leading to tinned copper "lead frames"; lead is toxic, so lead-free "lead frames" are now mandatory by RoHS. Another packaging technology -- chip level packaging. Like most packages, the volume of plastic dual in-line package is many times larger than the actual chip, and the chip size of chip level package is almost the same as the grain size; before slicing, the chip level package shell can be designed. After packaging, the chip needs to be tested to ensure that it is not damaged during the packaging process and the connection between grains and pins is correct. Then the model of the chip is marked by laser on the packaging shell.

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